Integrated circuits (ICs) continue to become faster, cheaper and smaller as the fabrication processes for forming ICs improve. One challenge in the fabrication of ICs is maintaining and improving yields as the technology changes and improves. For example, technology improvements may include the use of new materials (such as copper for metal interconnects), or new techniques (such as improved etching and chemical mechanical polishing (CMP) techniques) that may have an impact on the yield of the fabrication process. It is desirable to minimize the effects on yield and thereby improve cost-efficiency.
Prior art methods for monitoring processes and improving yield have some shortcomings. For instance, a “test key,” or a special test circuit, can be placed on the scribe line and used to monitor the process. The scribe line is located in an area on a wafer that is outside the area actively used by the integrated circuit being manufactured. The scribe line, however, is typically less than 10% of the total area, and therefore has limited ability to monitor the process. In particular, since the scribe line is outside the active chip area, problems occurring in the interior of the integrated circuit, especially highly localized problems, are not detected.
Other prior art techniques include running special test chips or test wafers through a process. A test chip may comprise special circuits that are useful for testing the process, and a test wafer may comprise one or more of such test chips. These techniques, however, have several disadvantages. Running a special test wafer greatly increases cost since the test wafer is only used to monitor the process, and will be discarded after serving that purpose. Typically, such test wafers are only used during development phases of the fabrication process, and not during production phases, due to this high cost. Similarly, using test chips also increases costs since the test chip occupies area on a wafer that cannot be used for actual chips. To mitigate this cost, only a sampling of wafer lots may include the test wafers, or only a small number of test chips will be used. The less frequent monitoring, however, increases the likelihood that a problem may be missed.
Another disadvantage of such techniques is that since the test chip design is not the same as the actual chip design, and in fact may be quite different, the test chip or test wafer may not detect all problems impacting yield for the actual chip designs. That is, the test chip may not be an ideal substitute for the actual chip, and yield problems may be associated with the specific circuits used in the actual design that are undetectable by the test chip. For instance, the test design and the actual design may have different metal densities that affect yield differently.
Therefore, a need exists for an accurate and cost-effective way to monitor an integrated circuit fabrication process.